1. Field of the Invention
The present invention generally relates to cache control methods and processor systems, and more particularly to a cache control method for controlling data sharing state (or conditions) when a synonym occurs in multi-level (or hierarchical) caches that are in an inclusion relationship, and to a processor system which employs such a cache control method.
2. Description of the Related Art
In a multi-processor system provided with multi-level caches that are in an inclusion relationship, if an index address of the cache is indexable by a real address, that is, if a Physical address Index Physical address Tag (PIPT) is employed, a number of bits usable as the index address becomes determined by a page size of the multi-processor system. Accordingly, a total capacity of the caches is equal to a product of the page size and a number of ways.
According to the PIPT, no synonym occurs because the index address of the cache is indexed by the real address and a match is detected by the real address. However, since a page boundary cannot be exceeded, there is a limit to the capacity per way.
As a method that does not generate such a limit to the capacity, there is a method which indexes a Translation Look-ahead Buffer (TLB) and obtains a real address corresponding to a virtual address, so as to make the indexing by the real address. However, this method indexes the cache based on the result of indexing the TLB, a cache latency is increased.
A Virtual address Index Physical address Tag (VIPT), which makes the indexing by the virtual address and not by the real address, has been proposed. According to the VIPT, the index address of the cache is indexed by the virtual address, and the match is detected by the real address. For this reason, it is possible to simply realize a capacity that exceeds the page boundary. However, although the VIPT can exceed the page boundary, the synonym occurs.
The synonym refers to a state where a single real address is referred by a plurality of virtual addresses. When the synonym occurs, the cache indexed by the plurality of virtual addresses is actually a single entity, but the data of the same real address is stored in a plurality of entries. Hence, in a case where the data stored in such a manner is to be updated, the data unity cannot be maintained unless the same data stored in each of the plurality of entries is updated.
For this reason, in the conventional multi-processor system, a secondary cache is indexed by the real address, and a portion of a virtual address with respect to this real address is held, so as to check the synonym. There is no time loss since the indexing of the TLB will be ended by the time the secondary cache is accessed. The secondary cache stores a pair of the real address and the virtual address at the time of a previous access, and makes a request to delete the entry with respect to the primary cache when a next access is made by a different combination. Accordingly, only one pair of the real address and the virtual address with respect to the real address always exists in the primary cache, and the data unity can be maintained.
FIG. 1 is a diagram for explaining a cache control operation at the time of an access when no synonym occurs. More particularly, FIG. 1 is a diagram for explaining the cache control operation for a case where data DATA of a real address PA(a) is registered at a virtual address VA(a) in a primary cache 1, and an access to the virtual address VA(a) is generated. A TLB 3 indicates that the data DATA of the real address PA(a) is registered in the primary cache 1 at the virtual address VA(a). In this case, a hit occurs since the virtual address VA(a) to which the access is generated matches the virtual address VA(a) that is registered in the primary cache 1.
FIG. 2 is a diagram for explaining a cache control operation at the time of an access when a synonym occurs. More particularly, FIG. 2 is a diagram for explaining the cache control operation for a case where the data DATA of the real address PA(a) is registered at a virtual address VA(b) in the primary cache 1, and an access to the virtual address VA(a) is generated, that is, the synonym occurs. In this case, a miss occurs because the virtual address VA(a) to which the access is generated does not match the virtual address VA(b) that is registered in the primary cache 1. The virtual address VA(b), the real address PA(a) and the data DATA are registered in correspondence with one another in a secondary cache 2. Accordingly, by indexing the secondary cache 2 by the real address PA(a) from the TLB 3, it can be seen that the data DATA of the real address PA(a) is registered in the primary cache 1 at the virtual address VA(b). Hence, by generating a delete request DEL requesting the primary cache 1 to delete the entry of the virtual address VA(b) and notifying the secondary cache 2 that the entry of the virtual address VA(b) of the primary cache 1 has been deleted, the entries of the virtual address VA(b) of the primary cache 1 and the secondary cache 2 are reregistered as the entries of the virtual address VA(a). Thereafter, the data DATA is transferred from the secondary cache 2 to the primary cache 1 as corresponding to the virtual address VA(a).
FIG. 3 is a diagram showing a state after the delete request DEL shown in FIG. 2 is processed when the synonym occurs. As shown in FIG. 3, the registration of the virtual address VA(b) is deleted from the primary cache 1 and the secondary cache 2, and only the virtual address VA(a) is registered in the primary cache 1 and the secondary cache 2.
Therefore, according to the conventional multi-processor system, the delete request DEL described above must be processed every time the synonym occurs, so as to eliminate the synonym state. Consequently, because of the need to carry out the process for eliminating the synonym state, there were problems in that a memory access time of the multi-processor system is long, and it is difficult to improve the memory utilization efficiency.
The inventors are aware of the following prior art.
Japanese Laid-Open Patent Application No.7-287668
Japanese Laid-Open Patent Application No.9-504627
Japanese Laid-Open Patent Application No.3-83150